The present invention relates to a method for forming semiconductor devices and integrated circuits containing such devices. More particularly, it relates to the formation of FET devices and especially to FET devices having self-aligned gates. Self-aligned gate field effect structures are well-known in the art. They are conventionally formed by processes which involve using a mask of a refractory material, i.e., a material which withstands high temperatures in the order of 1,000.degree. C. and above, as a masking material during the introduction of impurities which are to form the source and drain of the FET. Conventionally, this masking material may be material such as silicon in processes such as that described in U.S. Pat. No. 3,475,234, Kerwin et al., and U.S. Pat. No. 3,544,399, Dill, using polysilicon as such a masking material which remains in place in the gate region to eventually provide the gate electrode. Since such structures are insulated gate field effect transistors, IGFETs, there is a layer of an insulative material such as silicon dioxide beneath the silicon in the mask.
On the other hand, the refractory material may be an insulative material itself such as silicon nitride which may remain in place in the gate region to provide the gate insulation. Such methods are described in U.S. Pat. No. 3,544,858, Kooi, as well as in U.S. Pat. No. 4,058,887 DeWitt, filed Oct. 13, 1972. In these processes, the refractory material such as silicon nitride, or a composite of silicon nitride over silicon dioxide, serves to define the edges of the source and drain regions abutting the gate and which may then remain in place to function as the thin gate insulation in the IGFET. This is accomplished by thermally growing a thick oxide over the source and drain with the in-place silicon nitride serving the subsequent function of an oxidation blocking mask to to prevent any increase in the thickness of the thin gate insulation. Then, a conductive gate electrode is formed over the gate region with the thin silicon nitride layer or any other thin insulative layer formed after removal of the silicon nitride still functioning to define the functional gate region.
The major advance of the self-aligned gate was that it improved the positioning of the gate electrode and the gate insulation with respect to the source and drain. Previous to the self-aligned gate, the functional gate electrode, i.e., the portion of the gate electrode overlying the thin gate insulation had to be made too long relative to the channel length between the source and drain, i.e., this functional gate electrode considerably overlapped the source and drain. Hence, undesirable and excessive stray capacitance was developed between the functional gate electrode and the underlying source and drain. This substantially reduced the frequency response or speed of the FET devices in an integrated circuit.
While the self-aligned gate technologies in the prior art substantially reduced the extent of such undesirable functional gate overlap and thus substantially increased the integrated circuit switching time, it did not fully eliminate the problem of the functional gate electrode overlapping the source and drain. This was primarily due to the processing requirement, even with the self-aligned gate in place, of forming the source and drain by a diffusion step. Conventionally, this diffusion step may be carried out directly during the introduction of impurities forming the source and drain into the substrate with the self-aligning gate mask in place. Alternatively, these impurities may be introduced first by diffusion or ion implantation to form shallow surface regions followed by a high temperature drive-in step which then diffuses the source and drain deeper into the substrate. During such diffusion steps, the impurities would, of course, spread laterally beneath the gate masking member to some extent. Thus, the result would be some overlap of the source and drain by the functional gate electrode due to this lateral spreading during diffusion. This would still cause the undesirable stray capacitances described above which would reduce switching speeds and frequency responses of the devices.
It has been suggested in the prior art that self-aligned IGFETs may be formed by ion implantation alone without any diffusion step. U.S. Pat. No. 3,472,712 is representative of such a teaching. Certainly, structures formed in this manner will not have the undesirable gate overlap problem. However, such processes normally have the limitation that they are limited to source and drain regions which extend only to a depth of 2,000 A-3,000 A or less into the substrate. As a result, such source and drain regions have high resistances, i.e., sheet resistances in the order of 50 ohms per square. While such high sheet resistances are perfectly acceptable for many discrete FET device functions as well as for simpler FET integrated circuits, in the more complex FET integrated circuit technology where the source and drain regions or extensions thereof are used as part of the conductive interconnector network, much lower sheet resistances, in the order of from 8 to 10 ohms per square, become necessary. The art has conventionally achieved such low resistance source and drain regions by one of the above described diffusion techniques to form source and drain regions extending in the order of 1 micron (10,000 A) into the substrate. While it may be possible to form FETs with source and drain regions extending 10,000 A into the substrate to thus achieve the necessary low resistivity by ion implantation alone without subsequent diffusion, such ion implantation techniques would be expected to be quite complicated and would entail a series of ion implantations at a variety of energy and dosage levels.